Design and Development of Effective Multi-Level Cache Memory Model

Eze Val Hyginus Udoka; Martin Chinweokwu Eze; Enerst Edozie; Esther Chidinma Eze

doi:10.36079/lamintang.ijortas-0502.515

Design and Development of Effective Multi-Level Cache Memory Model

Eze Val Hyginus Udoka
Martin Chinweokwu Eze
Enerst Edozie
Esther Chidinma Eze

DOI: https://doi.org/10.36079/lamintang.ijortas-0502.515

Keywords: Access Time, Associativity, Cache Memory, Hit Rate, Main Memory

Abstract

An algorithm to determine the effectiveness and efficiency of a multi-level cache was developed in this paper. The developed model was used to test the efficiency rate, the relationships and the performance output level of a computer concerning the cache properties. This research paper showed that the level of cache and access time increases with the absolute hit rate but decreases with the relative hit rate. The number of cache levels varies directly with absolute access time and inversely with relative access time. The level one cache with set associativity of one has the highest access time and as the associativity and cache levels increase the memory access time decreases. The increase in the number of set associativity leads to an increase in cache performance and as well increases the performance speed of a computer.

Downloads

Download data is not yet available.

Author Biographies

Eze Val Hyginus Udoka

Department of Publication and Extension, Kampala International University. Kampala, Uganda.

Martin Chinweokwu Eze

Department of Electronic Engineering, University of Nigeria. Nsukka, Nigeria.

Enerst Edozie

Department of Electrical Engineering, Kampala International University, Kampala, Uganda.

Esther Chidinma Eze

Department of Publication and Extension, Kampala International University. Kampala, Uganda.

This is an open access article, licensed under CC-BY-SA

Published

2023-09-25

Downloads : 181

How to Cite

[1]

E. V. H. Udoka, M. C. Eze, E. Edozie, and E. C. Eze, “Design and Development of Effective Multi-Level Cache Memory Model”, International Journal of Recent Technology and Applied Science, vol. 5, no. 2, pp. 54-64, Sep. 2023.

Download Citation

Issue

Vol 5 No 2: September 2023

Section

Articles

References

P. Maniotis, S. Gitzenis, L. Tassiulas, and N. Pleros, “An optically-enabled chip–multiprocessor architecture using a single-level shared optical cache memory,” Optical Switching and Networking, vol. 22, pp. 54–68, 2016, doi: 10.1016/j.osn.2016.05.001.

M. Jhamb, R. K. Sharma, and A. K. Gupta, “A High Level Implementation and Performance Evaluation of Level – I Asynchronous Cache on FPGA,” Journal of King Saud University - Computer and Information Sciences, 2015, doi: 10.1016/j.jksuci.2015.06.003.

B. Cuesta, R. Alberto, R. Antonio, and D. Jose’, “Increasing the Effectiveness of Directory Caches by Avoiding the Tracking of Noncoherent Memory Blocks,” IEEE TRANSACTIONS ON COMPUTERS, vol. 62, no. 3, pp. 482–495, 2013.

Z. Fang et al., “Reducing cache and TLB power by exploiting memory region and privilege level semantics q,” Journal of Systems Architecture, vol. 59, no. 6, pp. 279–295, 2013, doi: 10.1016/j.sysarc.2013.04.002.

J. Díaz, J. L. Risco-martín, and J. M. Colmenar, “The Journal of Systems and Software Multi-objective optimization of energy consumption and execution time in a single level cache memory for embedded systems,” vol. 111, pp. 200–212, 2016, doi: 10.1016/j.jss.2015.10.012.

K. Markus and W. Christian, “An overview of Cache Optimization Techniques and Cache -Aware Numerical Algorithm.”

P. Maniotis, S. Gitzenis, L. Tassiulas, and N. Pleros, “An optically-enabled chip – multiprocessor architecture using a single-level shared optical cache memory,” Optical Switching and Networking, vol. 22, pp. 54–68, 2016, doi: 10.1016/j.osn.2016.05.001.

J. J. Valls, A. Ros, M. E. Gómez, and J. Sahuquillo, “The Tag Filter Architecture: An energy-efficient cache and directory design,” Journal of Parallel and Distributed Computing, pp. 1–10, 2016, doi: 10.1016/j.jpdc.2016.04.016.

A. Hsia, C. W. Chen, and T. J. Liu, “Energy-efficient synonym data detection and consistency for virtual cache,” Microprocessors and Microsystems, vol. 40, pp. 27–44, 2016, doi: 10.1016/j.micpro.2015.11.004.

A. Hsia, C. Chen, and T. Liu, “Microprocessors and Microsystems Energy-efficient synonym data detection and consistency for virtual cache,” vol. 40, pp. 27–44, 2016, doi: 10.1016/j.micpro.2015.11.004.

J. Díaz, J. L. Risco-martín, and J. M. Colmenar, “The Journal of Systems and Software Multi-objective optimization of energy consumption and execution time in a single level cache memory for embedded systems,” ELSEVIER, vol. 111, pp. 200–212, 2016, doi: 10.1016/j.jss.2015.10.012.

N. Miguel and D. Cerqueira, “Cache : Why Level It,” ICCA, pp. 19–26, 2016, [Online]. Available: http: //gec.di.uminho.pt/discip/minf/ac0102/0945CacheLevel.pdf

B. Cuesta, A. Ros, M. E. Gmez, A. Robles, and J. Duato, “Increasing the effectiveness of directory caches by avoiding the tracking of noncoherent memory blocks,” IEEE Transactions on Computers, vol. 62, no. 3, pp. 482–495, 2013, doi: 10.1109/TC.2011.241.

S. Mittal, “A survey of architectural techniques for improving cache power efficiency,” Sustainable Computing: Informatics and Systems, vol. 4, no. 1, pp. 33–43, 2014, doi: 10.1016/j.suscom.2013.11.001.

H. Han, T. Alexoudi, C. Vagionas, N. Pleros, and N. Hardavellas, “Pho: A Case for Shared Optical Cache Hierarchies,” in Proceedings of the International Symposium on Low Power Electronics and Design, 2021, vol. 2021-July. doi: 10.1109/ISLPED52811.2021.9502487.

Z. Fang et al., “Reducing cache and TLB power by exploiting memory region and privilege level semantics,” Journal of Systems Architecture, vol. 59, no. 6, pp. 279–295, 2013, doi: 10.1016/j.sysarc.2013.04.002.

N. Laoutaris, H. Che, and I. Stavrakakis, “The LCD interconnection of LRU caches and its analysis,” Performance Evaluation, vol. 63, no. 7, pp. 609–634, 2006, doi: 10.1016/j.peva.2005.05.003.

Y. Zhou, Z. Chen, and K. Li, “Second-level buffer cache management,” IEEE Transactions on Parallel and Distributed Systems, vol. 15, no. 6, pp. 505–519, 2004, doi: 10.1109/TPDS.2004.13.

J. P. D. Comput, J. J. Valls, A. Ros, M. E. Gómez, and J. Sahuquillo, “The Tag Filter Architecture : An energy-efficient cache and directory design,” ELSEVIER, pp. 1–10, 2016, doi: 10.1016/j.jpdc.2016.04.016.